Low leakage switches are of major importance in sample and hold systems with long hold times. Leakage currents become the dominant error source at elevated temperatures. Many electronic devices such as integrated semiconductor circuits sample an input or reference voltage on a capacitor. One side of the sampling capacitor is coupled to an input voltage through a sampling switch. The sampling switch is closed (conducting) and the sampling capacitor is charged during a sampling phase or sampling time. After sampling the voltage on the sampling capacitor, the sampling switch is opened (not conducting).
One purpose of sampling a voltage level is to extend the time period, known as hold phase or hold time, during which the sampling switch is not conducting. This aims to preserve the sampled voltage on the sampling capacitor as long as possible. Thus the charge on the sampling capacitor should be preserved. However, many characteristics of real integrated circuits adversely affect charge preservation. A major drawback is the leakage current through the sampling switches. A conventional approach to overcome this effect increases the capacitance value of the sampling capacitor. This increases the size of the capacitor. This is similar to increasing chip area and thereby cost of the integrated circuit. Larger capacitors can further increase power consumption if the same speed is maintained as for smaller capacitors. Other solutions aim to improve the sampling switches.
Sampling switches are implemented with transistors. In a CMOS technology a switch may be an NMOS, a PMOS transistor or a combination of both referred to as a transmission gate. MOS transistors have P-doped regions and N-doped regions which can form parasitic diodes. One of these diodes is referred to as backgate diode. Such a backgate diode couples the source or the drain of the transistor to the channel located opposite to the control gate. In a simplified model of a real MOS transistor a backgate diode may be located between drain and source of the transistor and the channel. In order to avoid leakage currents through these backgate diodes, the voltage level on the backgate or the channel is controlled to reversely bias the backgate diodes. Even with reverse bias a minimum saturation current can flow through the backgate diode and the voltage level on the sampling capacitor can change significantly.
FIG. 1 shows a prior art switching circuit designed to minimize charge loss on a sampling capacitor. This prior art circuit is disclosed in U.S. Pat. No. 6,603,295. The transistors and switches are controlled with signals from control circuit 2. The main sampling switch is implemented with transistor P1. The sampling capacitor is capacitor CS. Reference voltage generator 1 provides a reference voltage level at node VREFOUT. This is sampled and held on sampling capacitor CS. VREFOUT is also sampled through transistor P2 on a second capacitor C2. If the voltage level on capacitor C2 is equal to VREFS (both may initially be almost equal to VREFOUT) there is no voltage drop across backgate diode D1. Therefore there is no current through diode D1. There is also no voltage drop across backgate diode D2. The voltage level on capacitor C2 must also be preserved. Transistor P2 also has backgate diodes D3 and D4. Backgate diodes D3 and D4 are reverse biased to minimize leakage current. Therefore, the channel (backgate) of transistor P2 is adjusted to a specific voltage level. This is performed with bipolar transistor T1, current source CS and switch S2. If S2 is closed (conducting) the voltage level at the channel of transistor P2 is pulled to ground. If S2 is open (not conducting) the voltage rises close to supply voltage level VDD.
Although the circuit of FIG. 1 reduces the leakage current though backgate diodes of transistors P1 and P2 to a certain extent, charge preservation is not high enough for up-to-date low power applications with very long hold times. The circuit requires an extra bipolar transistor and consumes additional current through transistor T1.